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PhDPower electronicsResearch About 16 weeksMATLAB & Simulink

Multilevel Inverter Topologies for High-Voltage EV Drives

Model and compare multilevel inverter topologies for high-voltage EV drives: three-level NPC, T-type and cascaded H-bridge with battery modules. Quantify output quality, losses, dv/dt and neutral-point or module balancing against a two-level baseline over a drive cycle.

Tools: Simulink · Simscape Electrical

Multilevel Inverter Topologies for High-Voltage EV Drives: EV charger (EVSE) trainer demonstration at DIYguru
Representative photo from DIYguru's EV lab, not of this specific project.

The problem

As EVs move to 800 V and beyond, two-level inverters face high dv/dt, which stresses motor insulation and bearings, and switching losses that limit frequency. Multilevel inverters reduce voltage steps and harmonics and can use lower-voltage devices, and cascaded H-bridges can integrate battery modules with balancing. Each topology brings control problems such as neutral-point balance or module SOC balance, and their net benefit for traction is still being studied.

Objectives

  • Model a two-level baseline and three-level NPC and T-type inverters.
  • Model a cascaded H-bridge inverter with each cell fed by a battery module.
  • Implement carrier-based PWM schemes and neutral-point or SOC balancing.
  • Compare THD, dv/dt, losses and device count across topologies.
  • Evaluate topologies over a drive cycle with an FOC motor drive.

What you need

Tools and toolboxes

  • Simulink — Modulators, balancing controllers, FOC and scripted comparisons.
  • Simscape Electrical — Switching device models, clamping diodes, capacitors, Battery blocks and PMSM motor.
  • Stateflow — Optional: redundant-state selection logic for balancing. MATLAB Function blocks also work.

Software

  • MATLAB R2023b or later
  • Simulink
  • Simscape Electrical
  • WLTP or MIDC speed–time data and a vehicle model

Extra parts and data

  • Datasheets for devices at the chosen voltage classes (for example 1200 V and 650 V) — Loss comparisons between topologies are only meaningful with real device characteristics at the voltages each topology uses.

Key concepts

Neutral-point-clamped inverter
Each leg uses four switches and two clamping diodes to connect the output to the positive rail, negative rail or DC-link midpoint, giving three levels and halving voltage stress per device.
T-type inverter
A three-level topology with full-voltage outer switches and a bidirectional switch to the midpoint, which has lower conduction loss than NPC at moderate switching frequency.
Cascaded H-bridge
Several H-bridge cells in series per phase, each with its own isolated DC source such as a battery module, giving many levels and allowing module-level energy control.
Neutral-point balancing
In NPC and T-type inverters the midpoint current can drift the two capacitor voltages apart; redundant switching states or zero-sequence injection keep them balanced.

Step-by-step guide

  1. 1

    Define the drive and study scope

    Choose labelled example values: an 800 V nominal battery, a 150 kW PMSM traction drive, motor parameters from an earlier project scaled appropriately, and switching frequencies of 10 and 20 kHz. Define metrics: line-voltage THD, phase-current THD, maximum dv/dt per step, device count and voltage class, losses and drive-cycle energy. Fix the motor load and controller so that only the inverter changes.

    Checkpoint: A study plan listing topologies, metrics, operating points and cycle.

  2. 2

    Build the two-level baseline

    Build a two-level inverter with 1200 V class devices, SVPWM and the FOC drive. Measure THD, dv/dt and losses at several operating points with tabulated device losses. This baseline must be solid because all other results are relative to it. Use averaged loss models only after checking them against the switching model at a few points, record the simulation step size, and keep the motor and FOC parameters in one shared script.

    Checkpoint: Baseline metrics at all operating points recorded and consistent with earlier inverter work.

  3. 3

    Build NPC and T-type inverters

    Build three-level NPC and T-type legs with Simscape Electrical switches and clamping diodes, with a split DC link of two capacitors. Implement level-shifted (phase-disposition) carrier PWM. Check that each switch sees about half the DC-link voltage in NPC, and that the T-type outer switches see the full voltage. Check also that the T-type inner bidirectional switch is gated correctly in each state, since a wrong state can short the midpoint.

    Checkpoint: Line-voltage waveforms show five levels (line to line) and device voltage stresses match the topology.

  4. 4

    Implement neutral-point balancing

    Show the midpoint drift without balancing at low power factor and high modulation index. Then implement zero-sequence injection or redundant small-vector selection to balance the capacitor voltages. Measure the remaining midpoint ripple over a fundamental cycle at several operating points. Explain from the midpoint current why the imbalance grows in those conditions, and show the effect of capacitor size on ripple, since a larger capacitor reduces ripple but adds cost and volume.

    Checkpoint: Capacitor voltages stay balanced within a set tolerance at all tested points with balancing active.

  5. 5

    Build the cascaded H-bridge with battery modules

    Build a cascaded H-bridge with, for example, several cells per phase, each fed by a Simscape Electrical Battery block representing a module. Implement phase-shifted carrier PWM. Add an SOC balancing controller that adjusts each cell's share of the phase voltage based on its SOC, and start with deliberately unequal SOCs. Keep the number of cells modest at first so that the model runs quickly, then scale up.

    Checkpoint: Output has many voltage levels and module SOCs converge over time while the motor delivers the commanded torque.

  6. 6

    Compare output quality and dv/dt

    For all topologies at the same operating points, measure line-voltage and phase-current THD with fft over integer fundamental cycles and maximum voltage step per switching event. Present results as tables and spectra. Explain why the cascaded H-bridge can run each cell at a lower frequency for the same output quality. Include the motor-side current ripple at the same operating points, since it is what affects torque ripple and motor losses.

    Checkpoint: A comparison table of THD and dv/dt for all topologies at matched conditions.

  7. 7

    Compare losses

    Compute conduction and switching losses using appropriate device data for each topology (1200 V for two-level and T-type outer switches, 650 V for NPC devices and T-type inner switches, lower voltage for cascaded cells). Compare at matched output quality as well as matched switching frequency, because that is the fair comparison for multilevel inverters. Quote the device data source for each topology.

    Checkpoint: Loss comparison at matched frequency and at matched THD, with the best topology at each identified.

  8. 8

    Drive-cycle evaluation

    Using averaged loss models validated against the switching simulations, run a drive cycle through a vehicle model and the FOC drive for each topology. Report inverter energy loss and Wh/km, and for the cascaded H-bridge also the module SOC spread at the end of the cycle. Check that the averaged models match switching results at a few points of the cycle before trusting the totals, and record the remaining error in the results table.

    Checkpoint: Drive-cycle energy and balancing results for all topologies in one table.

  9. 9

    Discuss practical factors

    Compile device count, gate drivers, capacitor size, balancing complexity, fault tolerance and isolation requirements for each topology. Discuss charging implications, for example a cascaded H-bridge can reconfigure modules for 400 V or 800 V chargers. Keep the discussion qualitative where you have no data. Score each factor on a simple scale with a short reason, so that a reader sees the overall trade-off at a glance and can weight factors differently for their own application.

    Checkpoint: A topology comparison matrix covering both measured metrics and practical factors.

  10. 10

    Research write-up

    Document models, balancing methods, validation, comparisons and drive-cycle results. Release scripts where possible. State limitations such as no parasitic inductance, idealised gate drive and simplified battery models, and identify what hardware tests would confirm the key results. Compare with published topology comparisons for high-voltage traction, explain differences in assumptions, and state precisely what the study adds, such as battery-integrated balancing evaluated over a real drive cycle.

    Checkpoint: A thesis chapter draft with reproducible results and a clear contribution statement.

Testing & validation

  • Device voltage stress matches each topology.
  • Neutral-point balance maintained in NPC and T-type.
  • Module SOC balancing converges in the cascaded H-bridge.
  • THD, dv/dt and losses compared at matched conditions.
  • Drive-cycle energy comparison across topologies.

Expected results

A consistent comparison of two-level, NPC, T-type and cascaded H-bridge inverters for an 800 V EV drive, covering output quality, dv/dt, losses, balancing and drive-cycle energy, with a practical topology matrix.

Research angle for your PhD

Research questions: for 800 V EV traction, which multilevel topology offers the best trade-off between drive-cycle loss, dv/dt and complexity compared with a two-level SiC baseline, and can a battery-integrated cascaded H-bridge balance module SOC during driving without hurting efficiency? Metrics: cycle energy, THD, dv/dt, device count, balancing convergence. Baselines: a two-level inverter with SVPWM. Comparisons must be made at matched output quality with appropriate device data. A study combining fair topology comparison with integrated balancing over a drive cycle, with released models, can support a journal or conference paper.

Take it further

  • Add fault-tolerant operation by bypassing a failed cascaded cell.
  • Study model predictive control for NPC with balancing.
  • Integrate charging from an AC grid through the cascaded H-bridge.
  • Add common-mode voltage and bearing-current analysis.

Viva and review questions

Why does a three-level inverter reduce dv/dt?

Each switching event changes the output by half the DC-link voltage instead of the full voltage, so for the same switching speed the voltage step and its rate of change are halved.

What causes neutral-point imbalance in NPC?

Current drawn from the midpoint during some switching states charges one capacitor and discharges the other, and at certain power factors and modulation indices the average midpoint current is not zero.

Why compare at matched output quality?

Multilevel inverters reach the same THD at lower switching frequency, so comparing at the same frequency understates their loss advantage.

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