On-Board Charger Front End: Boost PFC Stage Simulation

The problem

Every on-board charger that plugs into a household socket must draw near-sinusoidal current in phase with the mains voltage, to meet harmonic standards and to make use of the outlet's rating. The boost PFC stage does this while producing a regulated DC link for the isolated DC–DC stage that follows. Designing it involves a fast current loop, a slow voltage loop and careful handling of the double-line-frequency ripple.

Objectives

• Size the boost inductor and DC-link capacitor for a single-phase PFC stage.
• Build a switching model with a diode bridge and boost converter.
• Implement average current-mode control with a slow outer voltage loop.
• Measure power factor, current THD and DC-link ripple.
• Test load steps and input voltage variation.

What you need

Key concepts

Power factor

Real power divided by apparent power; it falls when current is distorted (distortion factor) or shifted relative to voltage (displacement factor).

Average current-mode control

A fast inner loop forces the averaged inductor current to follow a reference shaped like the rectified mains voltage, scaled by the outer voltage loop output.

Double-line-frequency ripple

Single-phase input power pulses at 100 Hz on a 50 Hz supply, so the DC-link voltage carries a 100 Hz ripple; the voltage loop must be slow enough not to distort input current by following it.

Hold-up time

The time the DC link can supply the load after a mains dropout, set by C·(V1² − V2²)/(2·P).

Step-by-step guide

1. 1

   Set example specifications

   Choose labelled example values: 230 V RMS, 50 Hz input (range 180–264 V), 3.3 kW output, 400 V DC link, 65 kHz switching. Targets: power factor above 0.99 at full load, current THD below 5 per cent, DC-link ripple below 5 per cent peak-to-peak and a stated hold-up time. State which harmonic standard the THD target is meant to approximate, but treat the targets as design goals for the study rather than a compliance test.

   Checkpoint: A spec table with input range, power, DC-link voltage, frequency and quality targets.

2. 2

   Size the components

   Compute peak input current at minimum input voltage, choose the inductance for a ripple of 20–30 per cent of peak current at the worst-case point of the line cycle, and size the DC-link capacitor from both the 100 Hz ripple, ΔV ≈ P/(2π·100·C·Vdc), and the hold-up requirement. Choose standard values and record the rationale. Check the inductor's peak current against a candidate saturation rating at minimum input voltage and full load.

   Checkpoint: Script prints L, C, worst-case ripple and hold-up time meeting the spec.

3. 3

   Build the power stage

   Build an AC Voltage Source, a diode bridge, the boost inductor, a MOSFET, a fast boost diode, the DC-link capacitor and a resistive load (later a controlled current source representing the DC–DC stage). Use a fixed-step local solver with a step of about 100 ns, or ode23t with a small maximum step, and simulate several line cycles. Log input current, DC-link voltage and inductor current.

   Checkpoint: With a fixed duty, the DC link charges above the mains peak and the input current is visibly distorted, as expected without control.

4. 4

   Implement the current loop

   Create the current reference as the rectified input voltage, normalised, multiplied by the voltage-loop output. Design a PI current controller with a crossover around 5–10 kHz, well below 65 kHz, using the inductor plant Vdc/(L·s). Add input-voltage feed-forward of duty (1 − |vin|/Vdc) to reduce distortion near zero crossings. Check the inductor current at light load too, where it can become discontinuous near zero crossings and change the current-loop behaviour.

   Checkpoint: With a fixed reference amplitude, inductor current follows the rectified sine closely over the whole line cycle.

5. 5

   Implement the voltage loop

   Add a PI voltage loop on DC-link voltage with crossover around 10–20 Hz so that it largely ignores the 100 Hz ripple. Filter the measured voltage or add a notch at 100 Hz if needed. Add RMS input-voltage normalisation (dividing the reference by Vrms²) so that loop gain does not change with input voltage. Check the voltage loop margin at both minimum and maximum input voltage.

   Checkpoint: The DC link settles at 400 V with 100 Hz ripple close to the calculated value.

6. 6

   Measure power quality

   At full load and at 25, 50 and 75 per cent load, compute input power factor and current THD over an integer number of line cycles using fft. Plot input current against input voltage and the harmonic spectrum. Repeat at 180 V and 264 V input. Script the sweep with sim(). Save the sweep results to a file so that the power-quality table and plots are regenerated without rerunning every case.

   Checkpoint: Power factor and THD meet the targets at full load, with the trend at light load recorded.

7. 7

   Test transients

   Apply load steps from 50 to 100 per cent and back, and an input voltage step from 230 to 180 V. Measure DC-link overshoot and undershoot and recovery time, and check that input current stays sinusoidal during recovery. Also simulate a one-cycle mains dropout to verify hold-up time. Also check that the voltage loop does not saturate during the step, and if it does, add anti-windup and repeat the test to show the improvement.

   Checkpoint: DC-link deviations and recovery times recorded and within the chosen limits, and hold-up meets the spec.

8. 8

   Estimate losses and report

   Estimate bridge diode, MOSFET, boost diode and inductor losses using example datasheet values and compute efficiency at several loads. Write up the specifications, sizing, control design, power-quality results and transient tests. State that the model ignores EMI filtering and layout effects, and note that a bridgeless or totem-pole PFC would reduce bridge losses. Include the sizing script and the sweep scripts as an appendix.

   Checkpoint: A complete report with efficiency, power factor and THD tables reproducible from scripts.

Testing & validation

• Power factor and current THD at several loads and input voltages.
• DC-link ripple matches the 100 Hz ripple calculation.
• Load and line step responses within limits.
• Hold-up time verified with a mains dropout.
• Efficiency estimated at several loads.

Expected results

A working boost PFC model with average current-mode control that meets stated power-factor, THD and ripple targets, with transient and hold-up behaviour verified and losses estimated.

Take it further

• Model a totem-pole bridgeless PFC with fast switches and compare efficiency.
• Interleave two boost stages and compare inductor size and ripple.
• Add an EMI filter and check its interaction with the current loop.
• Connect the isolated DC–DC stage and battery to model the full charger.

Viva and review questions

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