DC Fast Charger Power Stage and Charging Curve Simulation

The problem

DC fast chargers must deliver tens of kilowatts with good power quality on the AC side and precise current and voltage control on the battery side, while the vehicle BMS changes its current request as the pack heats and fills. Understanding why a real charging curve tapers needs both the power stage and the battery modelled together. This project builds that chain.

Objectives

• Model a three-phase active front end with dq-frame current control and unity power factor.
• Model an isolated phase-shifted full-bridge or LLC DC–DC stage with output current and voltage control.
• Couple the charger to a pack model with temperature- and SOC-dependent current limits from the BMS.
• Reproduce a fast-charging curve with taper and thermal derating.
• Estimate stage efficiency and AC-side power quality.

What you need

Key concepts

dq-frame current control

Three-phase currents are transformed into a frame rotating with grid voltage, where they become DC quantities. PI controllers can then regulate active (d) and reactive (q) current with zero steady-state error.

Phase-shifted full bridge

An isolated DC–DC converter whose output is set by the phase shift between its two legs. It allows zero-voltage switching over a useful load range and is common in high-power chargers.

Charge-current request

The vehicle BMS tells the charger the maximum current it accepts, based on SOC, cell voltage and temperature. The charger follows this request, which is why the curve tapers.

Thermal derating

When pack temperature rises, the BMS lowers current to limit further heating and lithium plating risk, so a hot pack charges more slowly.

Step-by-step guide

1. 1

   Set ratings

   Use an example 50 kW charger: 415 V three-phase input, a 700 V DC link, and output range 200–500 V into an example 40 kWh, 350 V nominal pack. Targets: input power factor above 0.99 and current THD below 5 per cent at rated power, output current ripple under 2 per cent and a stage efficiency estimate. Write the BMS current-limit table as a function of SOC and temperature, as example values.

   Checkpoint: A parameter script and a plotted BMS current-limit map.

2. 2

   Build the active front end

   Model a two-level three-phase IGBT converter with an L or LCL filter and a DC-link capacitor. Implement a synchronous reference frame PLL, abc-to-dq transformation, d and q current PI controllers with cross-coupling decoupling, and an outer DC-link voltage loop. Use an average model for long charging runs and a switched model with a 1–2 µs discrete step for waveform and THD checks.

   Checkpoint: With a resistive load on the DC link, DC voltage holds at 700 V, the q current is zero and input current is in phase with voltage.

3. 3

   Build the DC–DC stage

   Model a phase-shifted full bridge at about 50 kHz with a high-frequency transformer, a secondary rectifier and an output LC filter. Alternatively model several parallel modules with interleaving. Implement an output current loop and an outer voltage loop combined through a Min selector, as in a CC–CV charger, so whichever limit is active controls the phase shift. Add a small leakage inductance in the transformer model, since it sets the zero-voltage switching range and the duty-cycle loss of the phase-shifted full bridge. Test the voltage loop separately with an open-circuit output.

   Checkpoint: Into a resistive load, output current follows a step reference with no overshoot beyond a few per cent.

4. 4

   Model the pack

   Build the pack from an example cell: series and parallel counts to reach 350 V and 40 kWh, an equivalent-circuit cell with OCV–SOC and resistance tables, and a lumped thermal mass with cooling. Simscape Battery can build this, or a single scaled equivalent-circuit block with I²·R heating works. Verify open-circuit voltage at several SOC levels against the cell data scaled by series count.

   Checkpoint: Pack OCV at 10, 50 and 90 per cent SOC equals the cell OCV times the series count.

5. 5

   Add the BMS request

   In a MATLAB Function or a 2-D Lookup Table, compute the maximum allowed current from present SOC and temperature, and the voltage limit from maximum cell voltage times series count. Pass these to the charger as current and voltage references. Update the request every 100 ms to mimic charger–vehicle communication. Do not model the protocol itself; the focus is the power and control behaviour.

   Checkpoint: As SOC rises in a test run, the current reference steps down following the map.

6. 6

   Run a full fast charge

   Using the average model, charge from 10 to 80 per cent SOC. Log AC power, DC output current and voltage, pack SOC and temperature. Plot power against SOC, the standard way fast-charging curves are shown. Record time from 10 to 80 per cent. Use a fixed-step discrete solver with a step chosen so the run finishes in reasonable time. Check energy conservation: integrated DC output energy should equal the pack energy change plus internal losses. Save the run so the derating cases can be overlaid on it later.

   Checkpoint: A charging curve with a plateau, then a taper as SOC and temperature rise, and a realistic 10–80 per cent time for the chosen rating.

7. 7

   Thermal derating cases

   Rerun the charge starting at pack temperatures of 15, 25 and 40 degC and with reduced cooling. Compare curves and charge times. Identify which part of the charge is limited by SOC, by temperature and by charger power. Explain why a pre-conditioned pack charges faster. Keep all other parameters identical between runs. Mark on each curve where the current is set by the SOC part of the BMS map and where by the temperature part, so the cause of each taper is visible.

   Checkpoint: Overlaid curves showing slower charging when the pack starts hot or cooling is poor.

8. 8

   Power quality and efficiency

   Switch to the switched model at a few fixed operating points (for example 25, 50 and 100 per cent power) and run long enough to reach steady state. Measure input THD with the powergui FFT and input power factor. Estimate efficiency from semiconductor conduction and switching losses, either from loss-aware blocks with datasheet tables or from post-processed currents and datasheet energies.

   Checkpoint: A table of THD, power factor and estimated efficiency at each operating point.

9. 9

   Report

   Present the topology, control design, pack and BMS models, the charging curves and the power-quality and efficiency results. Discuss which constraint limits charging time in each phase of the charge. State limitations: average models for long runs, a simplified thermal model, no communication protocol, and loss estimates rather than measurements. Note that high-voltage hardware is out of scope; this is a simulation study.

   Checkpoint: A report with the power-against-SOC curve, derating comparison and power-quality table, all regenerated by script.

Testing & validation

• Input power factor above 0.99 and THD below 5 per cent at rated power in the switched model.
• Average and switched models agree on averaged power and currents at a test point.
• Pack OCV verification against scaled cell data.
• Charging curve tapers in line with the BMS map, and energy into the pack matches the SOC change.

Expected results

A complete AC-to-battery fast charger model that reproduces a fast-charging curve with taper and thermal derating, with power-quality and efficiency figures at several operating points.

Take it further

• Replace the phase-shifted full bridge with an LLC resonant converter and compare efficiency.
• Add modular parallel units with power sharing.
• Add a pack pre-conditioning strategy and quantify its time saving.
• Model a Vienna rectifier front end.

Viva and review questions

Learn it at DIYguru

These DIYguru courses and programmes teach what this project needs.